<?xml version="1.0" encoding="UTF-8"?>
<modsCollection xmlns="http://www.loc.gov/mods/v3">
<mods ID="jin-etal-2025-verilocc">
    <titleInfo>
        <title>VeriLocc: End-to-End Cross-Architecture Register Allocation via LLM</title>
    </titleInfo>
    <name type="personal">
        <namePart type="given">Lesheng</namePart>
        <namePart type="family">Jin</namePart>
        <role>
            <roleTerm authority="marcrelator" type="text">author</roleTerm>
        </role>
    </name>
    <name type="personal">
        <namePart type="given">Zhenyuan</namePart>
        <namePart type="family">Ruan</namePart>
        <role>
            <roleTerm authority="marcrelator" type="text">author</roleTerm>
        </role>
    </name>
    <name type="personal">
        <namePart type="given">Haohui</namePart>
        <namePart type="family">Mai</namePart>
        <role>
            <roleTerm authority="marcrelator" type="text">author</roleTerm>
        </role>
    </name>
    <name type="personal">
        <namePart type="given">Jingbo</namePart>
        <namePart type="family">Shang</namePart>
        <role>
            <roleTerm authority="marcrelator" type="text">author</roleTerm>
        </role>
    </name>
    <originInfo>
        <dateIssued>2025-11</dateIssued>
    </originInfo>
    <typeOfResource>text</typeOfResource>
    <relatedItem type="host">
        <titleInfo>
            <title>Proceedings of the 2025 Conference on Empirical Methods in Natural Language Processing</title>
        </titleInfo>
        <name type="personal">
            <namePart type="given">Christos</namePart>
            <namePart type="family">Christodoulopoulos</namePart>
            <role>
                <roleTerm authority="marcrelator" type="text">editor</roleTerm>
            </role>
        </name>
        <name type="personal">
            <namePart type="given">Tanmoy</namePart>
            <namePart type="family">Chakraborty</namePart>
            <role>
                <roleTerm authority="marcrelator" type="text">editor</roleTerm>
            </role>
        </name>
        <name type="personal">
            <namePart type="given">Carolyn</namePart>
            <namePart type="family">Rose</namePart>
            <role>
                <roleTerm authority="marcrelator" type="text">editor</roleTerm>
            </role>
        </name>
        <name type="personal">
            <namePart type="given">Violet</namePart>
            <namePart type="family">Peng</namePart>
            <role>
                <roleTerm authority="marcrelator" type="text">editor</roleTerm>
            </role>
        </name>
        <originInfo>
            <publisher>Association for Computational Linguistics</publisher>
            <place>
                <placeTerm type="text">Suzhou, China</placeTerm>
            </place>
        </originInfo>
        <genre authority="marcgt">conference publication</genre>
        <identifier type="isbn">979-8-89176-332-6</identifier>
    </relatedItem>
    <abstract>Modern GPUs evolve rapidly, yet production compilers still rely on hand-crafted register allocation heuristics that require substantial re-tuning for each hardware generation. We introduce VeriLocc, a framework that combines large language models (LLMs) with formal compiler techniques to enable generalizable and verifiable register allocation across GPU architectures. VeriLocc fine-tunes an LLM to translate intermediate representations (MIRs) into target-specific register assignments, aided by static analysis for cross-architecture normalization and generalization and a verifier-guided regeneration loop to ensure correctness. Evaluated on matrix multiplication (GEMM) and multi-head attention (MHA), VeriLocc achieves 85–99% single-shot accuracy and near-100% pass@100. Case study shows that VeriLocc discovers more performant assignments than expert-tuned libraries, outperforming rocBLAS by over 10% in runtime.</abstract>
    <identifier type="citekey">jin-etal-2025-verilocc</identifier>
    <identifier type="doi">10.18653/v1/2025.emnlp-main.1538</identifier>
    <location>
        <url>https://aclanthology.org/2025.emnlp-main.1538/</url>
    </location>
    <part>
        <date>2025-11</date>
        <extent unit="page">
            <start>30252</start>
            <end>30262</end>
        </extent>
    </part>
</mods>
</modsCollection>

%0 Conference Proceedings
%T VeriLocc: End-to-End Cross-Architecture Register Allocation via LLM
%A Jin, Lesheng
%A Ruan, Zhenyuan
%A Mai, Haohui
%A Shang, Jingbo
%Y Christodoulopoulos, Christos
%Y Chakraborty, Tanmoy
%Y Rose, Carolyn
%Y Peng, Violet
%S Proceedings of the 2025 Conference on Empirical Methods in Natural Language Processing
%D 2025
%8 November
%I Association for Computational Linguistics
%C Suzhou, China
%@ 979-8-89176-332-6
%F jin-etal-2025-verilocc
%X Modern GPUs evolve rapidly, yet production compilers still rely on hand-crafted register allocation heuristics that require substantial re-tuning for each hardware generation. We introduce VeriLocc, a framework that combines large language models (LLMs) with formal compiler techniques to enable generalizable and verifiable register allocation across GPU architectures. VeriLocc fine-tunes an LLM to translate intermediate representations (MIRs) into target-specific register assignments, aided by static analysis for cross-architecture normalization and generalization and a verifier-guided regeneration loop to ensure correctness. Evaluated on matrix multiplication (GEMM) and multi-head attention (MHA), VeriLocc achieves 85–99% single-shot accuracy and near-100% pass@100. Case study shows that VeriLocc discovers more performant assignments than expert-tuned libraries, outperforming rocBLAS by over 10% in runtime.
%R 10.18653/v1/2025.emnlp-main.1538
%U https://aclanthology.org/2025.emnlp-main.1538/
%U https://doi.org/10.18653/v1/2025.emnlp-main.1538
%P 30252-30262

Markdown (Informal)

[VeriLocc: End-to-End Cross-Architecture Register Allocation via LLM](https://aclanthology.org/2025.emnlp-main.1538/) (Jin et al., EMNLP 2025)

• VeriLocc: End-to-End Cross-Architecture Register Allocation via LLM (Jin et al., EMNLP 2025)

ACL

• Lesheng Jin, Zhenyuan Ruan, Haohui Mai, and Jingbo Shang. 2025. VeriLocc: End-to-End Cross-Architecture Register Allocation via LLM. In Proceedings of the 2025 Conference on Empirical Methods in Natural Language Processing, pages 30252–30262, Suzhou, China. Association for Computational Linguistics.