Recent multimodal benchmarks have significantly expanded the evaluation of visual reasoning in vision-language models, but they primarily focus on holistic semantic understanding. Engineering problems can instead require models to connect visual regions with exact coordinate-level representations and reason over precise quantities. Semiconductor layout analysis is a representative example, yet this fine-grained multimodal grounding capability remains largely unexplored. We introduce ChipLayoutBench, the first benchmark for general semiconductor layout understanding, with text-only, image+metadata, and multimodal settings across diverse reasoning and grounding tasks. Evaluations of eight recent VLMs show that text-based representations achieve the strongest overall performance, while image+metadata inputs remain substantially more challenging. Moreover, combining both modalities often fails to improve over text alone and can even degrade performance, suggesting persistent difficulties in effectively grounding visual information with structured geometric representations. Dedicated VLM-specific tasks further expose these challenges in fine-grained cross-modal alignment and image-grounded reasoning. Our benchmark provides a domain-grounded testbed for advancing geometric reasoning and fine-grained multimodal grounding over structured engineering data.