Reinforcement learning (RL) post-training has emerged as a promising paradigm for LLM-based Verilog generation. However, existing RL credit assignment methods are either overly coarse (sequence-level GRPO) or fragmented (line-level methods), leading to severe misattribution as they ignore the characteristics of Verilog designs that are fundamentally structured through concurrent constructs and procedural control flows. To bridge this gap, we propose CirCA, a novel RL framework that performs credit assignment based on Atomic Logic Blocks (ALBs), the smallest semantically complete units of circuit logic. CirCA decomposes Verilog into ALBs, derives reliable rewards from signal-level feedback, and then constructs logic-enhanced signal dependency cones to localize erroneous ALBs, whose localized responsibilities are further incorporated into GRPO through asymmetric advantage correction. Extensive experiments show CirCA establishes a new state-of-the-art across multiple benchmarks among non-reasoning models, and even surpasses some cutting-edge reasoning models on complex tasks.